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SM8580AM Real-time Clock IC with 4-bit Interface and Built-in Temperature Sensor
OVERVIEW
The SM8580AM is a real-time clock IC based on a 32.768kHz crystal oscillator, which features a 4-bit parallel interface for communication with an external microcontroller. It comprises second-counter to year-counter clock and calendar circuits that feature automatic leap-year adjustment up to year 2099, alarm and timer interrupt functions, clock counter change detect functions, 30-second correction function, time error correction function, and built-in temperature sensor. The 4-bit parallel interface is compatible with general-purpose SRAM over a high-speed bus.
FEATURES
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PINOUT
(Top view)
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I I I I I I
I I I
High-speed bus 4-bit parallel interface Date, day, hour, minute, and second-counter presettable alarm interrupt 1/4096 seconds to 255 minutes presettable interval timer interrupt function 2 software-maskable alarm and timer interrupt outputs Clock counter change detect functions 4-digit western calendar display Automatic leap year correction up to year 2099 30-second adjust function -195 to +192ppm time error correction range Built-in temperature sensor (analog voltage output) 2.4 to 5.5V interface voltage range 1.6 to 5.5V clock voltage range 0.6A/3V (typ) current consumption
CE0N FCON FOUT VTEMP AIRQN TIRQN A0 A1 A2 A3 RDN VSS
1
24
VDD XT XTN NC NC NC CE1 D0 D1 D2 D3
12
13
WRN
ORDERING INFORMATION
Device SM8580AM Package 24-pin SSOP
PACKAGE DIMENSIONS
(Unit: mm)
5.40 0.20
7.80 0.30
10.05 0.20 10.20 0.30
5 0.15 - 0.0
+ 0.1
0.10 0.10
0.12 M
0.20 0.10
0.8
0.36 0.10 0.10
1.80
0 to 10 0.50 0.20
SEIKO NPC CORPORATION --1
1.90
SM8580AM
BLOCK DIAGRAM
Control line CG XT CD OSC XTN Divider Digital Trimming Controller
Clock and Calendar Counter
Alarm Register AIRQN TIRQN FOUT FCON A0 to A3 D0 to D3 WRN RDN Temperature Sensor CE0N CE1 BUS Interface Interrupt Control FOUT Control Timer Register FOUT Register Control Register
VDD
VSS
VTEMP
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SM8580AM
PIN DESCRIPTION
Number 1 Name CE0N I/O I Function1 Chip enable 0 input with built-in pull-up resistor. The SM8580AM can be accessed when CE0N is LOW and CE1 is HIGH. FOUT output frequency select control input (when CE1 is HIGH). 32.768kHz fixed frequency output when FCON is LOW. Output frequency determined by bit FD when FCON is HIGH (when FE bit is 1). Note that a HIGH-level voltage should be applied to FCON to avoid unwanted 32.768kHz output during backup. Frequency set register, frequency output (CMOS output) Temperature voltage output (analog output) Alarm interrupt output (N-channel open-drain output) Timer interrupt output (N-channel open-drain output)
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FCON
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3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FOUT VTEMP AIRQN TIRQN A0 A1 A2 A3 RDN VSS WRN D3 D2 D1 D0
O O O O I I I I I - I I/O I/O I/O I/O
Address inputs. Connect to the microcontroller address bus. The selected register address is input on this bus when accessing the SM8580AM (positive logic).
Read strobe input. Data can be read from SM8580AM when RDN is LOW and WRN is HIGH. An error will occur if both RDN and WRN are simultaneously LOW. Ground Write strobe input. Data can be written to SM8580AM when RDN is HIGH and WRN is LOW. An error will occur if both RDN and WRN are simultaneously LOW.
Data bus input/outputs. Connect to the microcontroller data bus.
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CE1
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Chip enable 1 input with built-in pull-down resistor. The SM8580AM can be accessed when CE0N is LOW and CE1 is HIGH. FOUT is in output mode when CE1 is HIGH, regardless of the state of CE0N. FOUT is high impedance when CE1 is LOW. No connection No connection No connection Oscillator output, with built-in oscillator capacitance CD Oscillator output, with built-in oscillator capacitance CG Supply
19 20 21 22 23 24
NC NC NC XTN XT VDD
- - - O I -
1. Connect a 0.1F capacitor between VDD and VSS.
SEIKO NPC CORPORATION --3
SM8580AM
FOUT Output and SM8580AM Access Relationship
CE0N HIGH LOW CE1 LOW LOW FCON x x LOW LOW HIGH HIGH HIGH HIGH LOW LOW LOW HIGH HIGH HIGH 0 1 High impedance FD bit select frequency output Yes Yes 0 1 0 1 High impedance FD bit select frequency output 32.768kHz output 32.768kHz output No No Yes Yes FE bit x x 0 1 FOUT output High impedance High impedance 32.768kHz output 32.768kHz output SM8580AM accessible No No No No
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0V
Parameter Supply voltage range Input voltage range Output voltage range Storage temperature range Symbol VDD VIN VOUT1 VOUT2 Tstg All inputs, D0 to D3 TIRQN, AIRQN FOUT, D0 to D3, VTEMP Condition Rating -0.3 to 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to 8.0 VSS - 0.3 to VDD + 0.3 -55 to 125 Unit V V V V C
Recommended Operating Conditions
VSS = 0V
Parameter Supply voltage range Clock supply voltage range Operating temperature range Symbol VDD VCLK Topr Condition Rating 2.4 to 5.5 1.6 to 5.5 -40 to 85 Unit V V C
SEIKO NPC CORPORATION --4
SM8580AM
DC Electrical Characteristics
VSS = 0V, VDD = 1.6 to 5.5V, Ta = -40 to 85C unless otherwise noted.
Rating Parameter Current consumption 1 Current consumption 2 Current consumption 3 Symbol IDD1 IDD2 IDD3 VDD = 5V VDD = 3V VDD = 5V Condition min CE0N = RDN = WRN = VDD, A0 to A3 = D0 to D3 = VDD or VSS, CE1 = FCON = VSS, AIRQN = TIRQN = FOUT = VDD, VTEMP output OFF (TEMP bit = 0) Ta = 25C, CE0N = RDN = WRN = VDD, A0 to A3 = D0 to D3 = VDD or VSS, CE1 = FCON = VSS, AIRQN = TIRQN = FOUT = VDD, VTEMP output ON (TEMP bit = 1) CE0N = CE1 = RDN = WRN = VDD, A0 to A3 = D0 to D3 = VSS, FCON = VSS, AIRQN = TIRQN = FOUT = VTEMP = Hi-Z, VTEMP output OFF (TEMP bit = 0), FOUT = 32kHz output, CL = 0pF CE0N = CE1 = RDN = WRN = VDD, A0 to A3 = D0 to D3 = VSS, FCON = VSS, AIRQN = TIRQN = FOUT = VTEMP = Hi-Z, VTEMP output OFF (TEMP bit = 0), FOUT = 32kHz output, CL = 30pF - - - typ 1.0 0.6 50 max 2.0 1.0 75 A A A Unit
Current consumption 4
IDD4
VDD = 3V
-
40
60
A
Current consumption 5
IDD5
VDD = 5V
-
3.0
7.5
A
Current consumption 6
IDD6
VDD = 3V
-
1.7
4.5
A
Current consumption 7
IDD7
VDD = 5V
-
8.0
20
A
Current consumption 8
IDD8
VDD = 3V
-
5.0
12
A
HIGH-level input voltage 1 LOW-level input voltage 1 HIGH-level input voltage 2 LOW-level input voltage 2 HIGH-level input voltage 3 LOW-level input voltage 3 Input leakage current Pull-up resistance 1 Pull-up resistance 2 Pull-down resistance 1 Pull-down resistance 2 Pull-down resistance 3 Pull-down resistance 4 HIGH-level output voltage 1 HIGH-level output voltage 2 HIGH-level output voltage 3 LOW-level output voltage 1 LOW-level output voltage 2 LOW-level output voltage 3 LOW-level output voltage 4 LOW-level output voltage 5 Output leakage current
VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 ILEAK RUP1 RUP2 RDWN1 RDWN2 RDWN3 RDWN4 VOH1 VOH2 VOH3 VOL1 VOL2 VOL3 VOL4 VOL5 IOZ
VDD = 4.5 to 5.5V, CE0N, FCON, RDN, WRN, A0 to A3, D0 to D3 VDD = 2.4 to 3.6V, CE0N, FCON, RDN, WRN, A0 to A3, D0 to D3 VDD = 1.6 to 5.5V, CE1 CE0N = VDD, CE1 = VSS, FCON = RDN = WRN = A0 to A3 = VDD or VSS VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 3V VDD = 5V VDD = 3V VDD = 3V VDD = 5V VDD = 3V IOH = -1mA, D0 to D3, FOUT IOH = -100A, D0 to D3, FOUT IOL = 1mA, D0 to D3, FOUT IOL = 100A, D0 to D3, FOUT IOL = 1mA, AIRQN, TIRQN CE0N = VSS
2.2 VSS - 0.3 0.8VDD VSS - 0.3 0.8VDD VSS - 0.3 -0.5 75 150 20
- - - - - - - 150 300 40 85 60 110 - - - - - - - - -
VDD + 0.3 0.8 VDD + 0.3 0.2VDD VDD + 0.3 0.2VDD 0.5 300 600 80 170 120 220 5.0 3.0 3.0 0.5 0.8 0.1 0.25 0.4 0.5
V V V V V V A k k M M k k V V V V V V V V A
CE1 = VDD
42.5 30
CE1 = 0.5V 55 4.5 2.0 2.9 0 0 0 0 0 -0.5
D0 to D3, AIRQN, TIRQN, FOUT, VOUT = VDD or VSS
SEIKO NPC CORPORATION --5
SM8580AM
Terminal Capacitance Characteristics
Ta = 25C, f = 1MHz
Rating Parameter Address input capacitance Data output capacitance Symbol CADD CDATA Condition min A0 to A3 D0 to D3 - - typ - - max 8 15 pF pF Unit
Oscillator Characteristics
Ta = 25C, NPC's standard crystal (CI = 30k, CL = 10pF) unless otherwise noted.
Rating Parameter Oscillator start time Oscillator stop voltage Frequency voltage characteristic Frequency accuracy Input capacitance Output capacitance Symbol tSTA VSTO f/V IC CG CD VDD = 1.6 to 5.5V VDD = 3.0V VDD = 3.0V VDD = 3.0V Condition min VDD = 1.6 V - - -2 -20 - - typ - - - - 15 10 max 3.0 1.5 +2 +20 - - s V ppm/V ppm pF pF Unit
AC Characteristics (1)
VSS = 0V, Ta = -40 to 85C unless otherwise noted.
Rating Parameter Symbol Condition min FOUT duty Duty VDD = 5V 10% VDD = 3V 10% Oscillator failure detection time tOSC VDD = 5V 10% VDD = 3V 10% 40 40 10 10 max - - - - min 60 60 - - % % ms ms Unit
SEIKO NPC CORPORATION --6
SM8580AM
AC Characteristics (2)
VDD = 2.4 to 3.6V, VSS = 0V, Ta = -40 to 85C, inputs VI = 0.5VDD, outputs VO = 0.5VDD, output load capacitance CL = 100pF (tACC, tACS, tARD)
Rating Parameter Read cycle time Address access time CE access time RD access time CE output set time CE output floating RD output set time RD output floating Output hold time Write cycle time Chip select time Address valid to end-of-write Address setup time Address hold time Write pulsewidth Input data set time Input data hold time Symbol min tRC tACC tACS tARD tCLZ tCHZ tOLZ tOHZ tOH tWC tCW tAW tAS tWR tWP tDW tDH 150 - - - 5 - 5 - 10 150 140 140 0 0 130 80 0 max - 150 150 100 - 60 - 60 - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
VDD = 4.5 to 5.5V, VSS = 0V, Ta = -40 to 85C, inputs VI = 0.5VDD, outputs VO = 0.5VDD, output load capacitance CL = 100pF (tACC, tACS, tARD)
Rating Parameter Read cycle time Address access time CE access time RD access time CE output set time CE output floating RD output set time RD output floating Output hold time Write cycle time Chip select time Address valid to end-of-write Address setup time Address hold time Write pulsewidth Input data set time Input data hold time Symbol min tRC tACC tACS tARD tCLZ tCHZ tOLZ tOHZ tOH tWC tCW tAW tAS tWR tWP tDW tDH 85 - - - 3 - 3 - 5 85 70 70 0 0 65 35 0 max - 85 85 45 - 30 - 30 - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
SEIKO NPC CORPORATION --7
SM8580AM Data read
t RC
A0 to A3
t ACC t ACS
CE0N
t OH
t CLZ
CE1
t CHZ
t ACS t CLZ t ARD t CHZ
RDN
t OLZ
D0 to D3
t OHZ
Data write
CE control
t WC
A0 to A3
t AW t CW
CE0N*
t WR
t AS
CE1
WRN
t DW
D0 to D3
t DH
WR control
t WC
A0 to A3
t AW
CE0N
t WR
t AS
CE1
t WP
WRN*
t DW
D0 to D3
t DH
*: When writing data, CE0N or WRN should be held HIGH level while the address changes.
SEIKO NPC CORPORATION --8
SM8580AM
Temperature Sensor
VSS = 0V, Ta = -40 to 85C unless otherwise noted.
Rating Parameter Symbol Condition min Temperature sensor output voltage Output accuracy Temperature sensitivity1 Linearity2 Temperature detection range Output resistance3 Output load capacitance Output load resistance Response time VOUT TACR VSE NL TOPR RO CL RL tRSP Ta = 25C, VSS reference output voltage, VDD = 2.7 to 5.5V, VTEMP Ta = 25C -40C Ta 85C, VDD = 2.7 to 5.5V -40C Ta 85C, VDD = 2.7 to 5.5V NL 2.0%, VDD = 2.7 to 5.5V Ta = 25C, VDD = 2.7 to 5.5V, VTEMP VDD = 2.7 to 5.5V VDD = 2.7 to 5.5V VDD = 3.0V, RL = 500k, CL = 100pF - - -7.3 - -40 - - 500 - max 1.470 - -7.8 - - 1.0 - - - min - 5 -8.3 2.0 85 3.0 100 - 200 V C mV/C % C k pF k s Unit
1. Temperature sensitivity VSE = (V(85C) - V(-40C) ) / 125 [mV/C] 2. Linearity NL = a / b x 100 [%], where a = maximum deviation between the measured value and the approximated value of VTEMP, and b = difference between the measured values at temperatures of -40 and 85C
VTEMP(V) a V (-40 C) a b Approximate value Measured value
a -40 C
V (85 C) Ta
0C
85 C
3. Output resistance RO = V1 / I1 []
SM8580A VTEMP 1M I1 OP AMP V1
SEIKO NPC CORPORATION --9
SM8580AM
Backup Transfer and Return
Parameter1 Supply voltage falling edge CE setup time Supply voltage fall time Supply voltage rise time Supply voltage rising edge CE hold time Rating Symbol tCD tF tR tCU (VDD - VCLK) 2.0V (VDD - VCLK) > 2.0V Condition min 0 2 50 1 0 max - - - - - min - - - - - s s/V s/V s/V s Unit
1. Before switching the supply, confirm that the chip enable CE1 is LOW and that SM8580AM is deselected.
VDD
VCLK tCD
CE1
VIL
tF tCU
tR
VIL
Backup mode
SEIKO NPC CORPORATION --10
SM8580AM
FUNCTIONAL DESCRIPTION
Register Tables
Bank 0 (clock, calendar registers)
Address 0 Second registers 1 2 Minute registers 3 4 Hour registers 5 6 7 Date registers 8 9 Month registers A B C Year registers D E F Control register 800 TEST Bank SEL1 400 TEMP Bank SEL0 200 2000 STOP 100 1000 BUSY/ ADJ
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Bank 2 (digital correction, timer registers)
Bit 0 1 10 1 10 1 10 1 1 10 1 10 1 10 Address 0 1 2 3 4 5 6 7 Register Digital correction registers - - Timer counter set registers Timer counter output registers Timer setting - - - - - Timer control Control register Bit 3 DT3 DT_ON # # 8 128 8 128 TE # # * * * TEST Bank SEL1 Bit 2 DT2 DT6 # # 4 64 4 64 TI/TP # # * * * TEMP Bank SEL0 Bit 1 DT1 DT5 # # 2 32 2 32 TD1 # # * * * TF STOP Bit 0 DT0 DT4 # # 1 16 1 16 TD0 # # * * * TIE BUSY/ ADJ
Register
Bit 3 8 FOS 8 # 8 #
Bit 2 4 40 4 40 4 # 4 4 # 4 # 4 40
Bit 1 2 20 2 20 2 20 2 2 20 2 # 2 20
Day of week register
# 8 # 8 # 8 80
8 9 A B C D E F
Bank 1 (alarm, FOUT registers)
Address 0 Second registers 1 2 Minute registers 3 4 Hour registers 5 6 7 Date registers 8 9 A B C D E F - - CE1 control FOUT divider set register FOUT frequency set register Alarm control Control register AE * * * * * 20 * * * FD1 FD4 AF STOP 10 * * * FD0 FD3 AIE BUSY/ ADJ Day of week register AE AE 8 * 4 4 20 2 2 10 AE 8 40 4 20 2 10 1 AE 8 40 4 20 2 10 1 Register Bit 3 8 Bit 2 4 Bit 1 2 Bit 0 1
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1
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1
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CTEMP CDT_ON # FE TEST Bank SEL1 FD2 # TEMP Bank SEL0
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All bits in register F and bits 2 to 3 in register E are common to all register banks. When alarm interrupts are not used, registers 0 to 8 in bank 1 can be used as RAM (total 36 bits). When timer interrupts are not used, registers 4 to 5 in bank 2 can be used as RAM (total 8 bits). When digital correction is not used, registers 0 to 1 in bank 2 can be used as RAM, excluding bit 3 (DT_ON) in register 1 (total 7 bits). The BUSY/ADJ bit function is BUSY when reading, and ADJ when writing. The BUSY flag is set to 1 an interval of 244s before clock counter update timing. Registers 6 and 7 in bank 2 are read-only registers, and cannot be written to. When power is applied, all register bits are undefined, with the exception of bits FOS, TEST and TEMP. Accordingly, these bits need to be initialized. TEST and TEMP are automatically reset to 0 and FOS is automatically reset to 1 when power is applied. Bits marked # are all read-only bits fixed to 0. These bits cannot be written to. Bits marked * can be used as RAM bits.
SEIKO NPC CORPORATION --11
SM8580AM
Control Registers (All Banks, Register E (bits 2, 3) and F)
Bank 0, 1, 2 F
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Address E
Bit 3 TEST Bank SEL1
Bit 2 TEMP Bank SEL0
Bit 1
Bit 0
STOP
BUSY/ADJ
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TEST bit Factory test bit. This bit should be set to 0. Take care when writing to other E register bits not to accidentally write 1 to the TEST bit. Automatically resets to 0 when power (VDD) is applied. TEMP bit When set to 1, it enables the temperature sensor voltage output on pin VTEMP. When set to 0, VTEMP is high impedance. Automatically resets to 0 when power is applied. Bank SEL bits Bank select bits for read/write operations.
Bank SEL1 0 0 1 1 Bank SEL0 0 1 0 1 Accessed bank Bank 0 Bank 1 Bank 2 Bank 1
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STOP bit When set to 1, the clock 32Hz frequency divider counter stops and is reset. When set to 0, the clock restarts. BUSY/ADJ bit This bit functions as a BUSY function in read mode, and as an ADJ function in write mode. * ADJ function (30 seconds adjust bit) The following processes are operated when a logic 1 is written to ADJ, however a logic 0 cannot be written to. Second registers are reset to 00 and minute registers not incremented when the clock counter is reset and the second registers are currently 00 to 29. Second registers are reset to 00 and minute registers are incremented when the clock counter is reset and the second registers are currently 30 to 59. The ADJ bit is automatically reset to 0 a maximum of 244s after it is set to 1. * BUSY function (second registers increment or 30 seconds adjust busy indicator bit) When BUSY is 1, the counters are being updated (incremented or reset). To read or write to clock and calendar registers, the BUSY flag has to be 0. If reading data when BUSY is set to 1, there is a possibility that incorrect (intermediate) data will be output. BUSY is set to 1 under the following two circumstances.
Normal seconds digit carry
30 seconds digit adjust (when ADJ is set to 1)
244s Carry complete
max 244s Setting ADJ bit to "1" Adjust function complete
SEIKO NPC CORPORATION --12
SM8580AM
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Function operation table
Bit STOP 0 0 1 1 ADJ 0 1 0 1 Clock Operating Adjust1 Stopped Stopped/adjust2 Timer Operating3 Operating4 Operating/stopped5 Operating/stopped5 Function Alarm Operating Operating6 Stopped Stopped FOUT Operating7 Operating8 Operating/stopped9 Operating/stopped9
1. 30 seconds adjust function 2. The clock stops, and the 30 seconds adjust function operates. 3. If the timer source clock frequency is 1Hz, the timer cycle changes when the digital correction function is used. If the timer source clock frequency is 64Hz, the timer cycle is not affected when the digital correction function is used. 4. If the timer source clock frequency is 1Hz, the timer cycle changes. If the timer source clock frequency is 64Hz, the timer cycle does not change. 5. If the timer source clock frequency is 1Hz, the timer is stopped. If the timer source clock frequency is 64Hz, the timer operates. 6. An alarm interrupt is not generated by the 30-second adjust function (ADJ) even if all other alarm conditions are met. However, an alarm interrupt is generated 1 second later if the alarm conditions are still met. 7. If the FOUT source clock frequency is 1Hz, the cycle changes when the digital correction function is used. If the FOUT source clock frequency is 32Hz, the cycle is not affected when the digital correction function is used. 8. If the FOUT source clock frequency is 1Hz, the cycle changes. If the FOUT source clock frequency is 32Hz, the cycle does not change. 9. If the FOUT source clock frequency is 1Hz, the timer is stopped. If the FOUT source clock frequency is 32Hz, the timer operates.
SEIKO NPC CORPORATION --13
SM8580AM
Clock and Calendar Registers (Bank 0, Registers 0 to E)
Clock counters (registers 0 to 5)
Bank Address 0 Second registers 1 2 0 3 4 Hour registers 5
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Register
Bit 3 8 FOS 8
Bit 2 4 40 4 40
Bit 1 2 20 2 20 2 20
Bit 0 1 10 1 10 1 10
Minute registers 8 4
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Data in these registers is interpreted in BCD format. For example, if the seconds registers 1 and 0 contain 0101 1001, then the contents are interpreted as the value 59 seconds. Hour register contents are values expressed in 24-hour mode.
FOS (oscillator failed detect bit (register 1, bit 3))
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The FOS bit is the oscillator failure flag. It indicates that the oscillator has stopped due to supply voltage reduction during operation. It is set to 1 when the oscillator stops, and remains 1 until reset by writing 0 to FOS. It is not affected by the function of other bits. A 1 is written to FOS when power is applied.
Day-of-week counter (register 6)
Bank 0
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Address 6
Register Day of week register
Bit 3
Bit 2 4
Bit 1 2
Bit 0 1
The day-of-week register contains values representing the day of the week as shown in the following table.
Bit 2 0 0 0 0 1 1 1 Bit 1 0 0 1 1 0 0 1 Bit 0 0 1 0 1 0 1 0 Weekday Sunday Monday Tuesday Wednesday Thursday Friday Saturday
Calendar registers (registers 7 to E)
Bank Address 7 Date registers 8 9 Month registers A 0 B C Year registers D E
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Register
Bit 3 8
Bit 2 4
Bit 1 2 20
Bit 0 1 10 1 10
8
4
2
8 80 800 TEST
4 40 400 TEMP
2 20 200 2000
1 10 100 1000
Registers B to E are 4 digits forming the western calendar year. Leap-year adjustment is automatic for years 1901 to 2099.
SEIKO NPC CORPORATION --14
SM8580AM
Alarm Registers (Bank 1, Registers 0 to 8, E)
Alarm control register (register E)
Bank 1
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Address E
Register Alarm control
Bit 3
Bit 2
Bit 1 AF
Bit 0 AIE
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AF bit (alarm flag) The AF bit is set to 1 when an alarm event is occurred, when the settings in the alarm set registers (bank 1, registers 0 to 8) match the settings in the day, clock and calendar registers (bank 0, registers 0 to 8). A logic 0 cannot be written to AF for 1s maximum after AF is set to 1. The AF bit remains 1 until reset by writing 0 to AF. A logic 1 cannot be written to AF. AIE bit (alarm interrupt enable) This bit enables the output on AIRQN when an alarm interrupt is occurred. If the AIE is not set to 1, then no output occurs even if the AF bit is set to 1. The AIRQN output is high impedance when AIE is set to 0.
Alarm set registers (registers 0 to 8)
Bank Address 0 Second registers 1 2 Minute registers 3 1 4 Hour registers 5 6 7 Date registers 8
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Register
Bit 3 8 AE 8 AE 8 AE
Bit 2 4 40 4 40 4 * 4 4 *
Bit 1 2 20 2 20 2 20 2 2 20
Bit 0 1 10 1 10 1 10 1 1 10
Day of week register
AE 8 AE
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These registers set the alarm time and date. When the corresponding bank 0 registers match these bank 1 registers, an alarm event occurs and AIRQN goes LOW if AIE is set to 1. An alarm can be set for date, day-of-week, hour, minute, and second. Each of these have a corresponding AE (alarm enable) bit which allows easy combination to create alarm events every second, every minute, hourly, daily, and weekly alarms. Note that alarms cannot be set for multiple days within the same week (such as an alarm on Mondays and Fridays only). When an AE bit is set to 0, the relevant register and corresponding bank 0 register are compared. When an AE bit is set to 1, the data is disregarded and all bits considered as "don't care" bits.
Day-of-week alarm bits (register 6)
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The day-of-week register contains values representing the day of the week as shown in the following table.
Bit 2 0 0 0 0 1 1 1 Bit 1 0 0 1 1 0 0 1 Bit 0 0 1 0 1 0 1 0 Weekday Sunday Monday Tuesday Wednesday Thursday Friday Saturday
SEIKO NPC CORPORATION --15
SM8580AM
Timer Registers (Bank 2, Registers 4 to 8, E)
Timer control registers (registers 8, E)
Bank 2 E
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Address 8
Register Timer setting Timer control
Bit 3 TE
Bit 2 TI/TP
Bit 1
Bit 0
TF
TIE
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TE bit (timer enable) Timer countdown stop/start control bit. When set to 1, the timer starts counting down. When set to 0 during countdown, the timer stops. TF bit (timer flag) The timer flag is set to 1 when the timer counter counts down to zero, occurring a timer event. A logic 0 cannot be written to TF for 1s maximum after TF is set to 1. It is held at 1 until 0 is written to this bit. A 1 cannot be written to TF. TIE bit (timer interrupt enable) This bit enables the timer interrupt output on TIRQN when a timer event is occurred. If the TIE is not set to 1, then no output occurs even if the TF bit is set to 1. The TIRQN output is high impedance when TIE is set to 0. TI/TP bit (level/periodic interrupt mode select bit) Sets the timer interrupt signal output mode. The SM8580AM supports two timer function modes. * TI/TP = 0 (level interrupt mode) When a timer interrupt is occurred, TIRQN goes LOW (if TIE = 1) and TF is set to 1. TIRQN remains LOW and TF is held at 1 until a 0 is written to the TF bit. The timer operates by counting down until the data is zero, then the TE bit is cleared and the count stops automatically. However, if the timer is started when the TF bit is 1, then the TE bit is not cleared. The timer count register contents remain zero after the count down stops. * TI/TP = 1 (periodic interrupt mode) When a timer interrupt is occurred, TIRQN goes LOW (if TIE = 1) and TF is set to 1. TIRQN subsequently goes high impedance after a fixed interval, but TF is held at 1 until a 0 is written to the TF bit. The timer operates by counting down until the data is zero, then the timer register data is reloaded automatically after a fixed interval, and the countdown restarts. This mode can be used as a repetitive interval timer.
Timer source clock set register (register 8)
Bank 2
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Address 8
Register Timer setting
Bit 3
Bit 2
Bit 1 TD1
Bit 0 TD0
The register 8 bits 0 and 1 set the timer source clock to one of four frequencies listed in the following table.
TD1 0 0 1 1 TD0 0 1 0 1 Timer source clock 4096Hz 64Hz 1Hz 1/60Hz (1 minute)
SEIKO NPC CORPORATION --16
SM8580AM Timer counter set registers (registers 4 to 7)
Bank Address 4 Timer counter set registers 5 2 6 Timer counter output registers 7
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Register
Bit 3 8 128 8 128
Bit 2 4 64 4 64
Bit 1 2 32 2 32
Bit 0 1 16 1 16
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Registers 4 and 5 set an 8-bit presettable binary down-counter value for the timer interrupt function. The value of the count can be determined by reading the values of registers 6 and 7 during the count. The presettable binary down-counter is updated when the data is written to registers 4 and 5. The data written to registers 4 and 5 are stored and are not changed until replacement data is written. This allows these bits to function as RAM bits if the timer interrupt mode is not used (when TIE = 0). When TE is set to 1, periodic interrupts are not output on TIRQN, even if registers 4 and 5 are set to zero.
Timer interrupt function example
Example of an hourly periodic timer interrupt
Bank Address 4 Timer counter set registers 5 2 8 E
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Register
Bit 3 1 0
Bit 2 1 0 1 TEMP
Bit 1 0 1 1 TF
Bit 0 0 1 1 1
Timer set register Timer control
TE TEST
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The timer error, when the timer starts, is an interval of 0 to 1 cycles of the source clock selected during the first timer operation. Specifically, if the source clock is 1/60Hz (1 minute cycle) and with TE bit = 1 write timing, the maximum error that can occur is +60 seconds. Also, timer operations that last less than 1 source clock cycle are not normally counted. The timer count start timing in data write mode occurs on the first falling edge of the source clock after the WRN rising edge that sets the TE bit, shown in the timing diagram below. Also, when the timer is stopped by changing the setting of TE bit from 1 to 0, the count stops after the countdown operation a maximum of 1 clock cycle of the selected source clock later. Specifically, if the source clock is 1/60Hz (1 minute cycle) and with TE bit = 0 write timing, the timer count is decremented and the timing stops a maximum of 60 seconds later. At this point, there is a possibility that the timer count has decremented to zero and generated an interrupt. Therefore, if interrupts are not required, the TIE interrupt enable bit should be set to avoid unwanted interrupts from occurring.
Address 8
WRN pin D3 pin Timer source clock
TE
Timer
TE="1"
"0" Timer start
Timer stop TE="0" "1"
SEIKO NPC CORPORATION --17
SM8580AM
CE1 Control Register (Bank 1, Register B)
Bank 1
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Address B
Register CE1 control
Bit 3 CTEMP
Bit 2 CDT_ON
Bit 1
Bit 0
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I
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This register determines whether the temperature sensor function and digital correction function in combination with the CE1 input pin. CTEMP determines the temperature sensor operation, and CDT_ON determines the digital correction function operation. CTEMP bit When CTEMP is set to 0, the temperature sensor operates only when the CE1 pin is HIGH. When CTEMP is set to 1, the temperature sensor operates without any relationship to the CE1 input state. Note that the temperature sensor operation also depends on the bank 2 TEMP bit to be active. CDT_ON bit When CDT_ON is set to 0, the digital correction function operates only when the CE1 pin is HIGH. When CDT_ON is set to 1, the digital correction function operates without any relationship to the CE1 input state. Note that the digital correction function also depends on the bank 2 DT_ON bit to be active. Function operation tables
CE1 pin x LOW HIGH LOW HIGH CTEMP bit x 0 0 1 1 TEMP bit 0 1 1 1 1 Temperature sensor Not operating Not operating Operating Operating Operating
CE1 pin x LOW HIGH LOW HIGH
CDT_ON bit x 0 0 1 1
DT_ON bit 0 1 1 1 1
Digital correction Not operating Not operating Operating Operating Operating
SEIKO NPC CORPORATION --18
SM8580AM
Frequency Set Registers (Bank 1, Registers C, D)
Bank 1 D
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Address C
Register FOUT divider set register FOUT frequency set register
Bit 3
Bit 2 FD2
Bit 1 FD1 FD4
Bit 0 FD0 FD3
FE
FD3, FD4 bit FOUT source clock frequency set bits.
FD4 0 0 1 1 FD3 0 1 0 1 Source clock 32768Hz 1024Hz 32Hz 1Hz
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FD0 to FD2 bits Frequency divider set bits for the FOUT source clock set by FD3 and FD4.
FD2 0 0 0 0 1 1 1 1 FD1 0 0 1 1 0 0 1 1 FD0 0 1 0 1 0 1 0 1 Frequency divider ratio 1/1 1/2 1/3 1/6 1/5 1/10 1/15 1/30 FOUT output duty 1/2 1/2 1/3 1/2 1/5 1/2 1/3 1/2
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FE bit FOUT frequency signal set by FD0 to FD4 output enable bit. When FCON is HIGH and FE is set to 1, then the frequency signal set by FD0 to FD4 is output on FOUT. When FE is set to 0, the FOUT output is high impedance. When FCON is LOW, a standard 32.768kHz signal is output on FOUT without reference to the settings in the C and D registers.
SEIKO NPC CORPORATION --19
SM8580AM
Digital Correction Registers (Bank 2, Registers 0, 1)
Bank 2 1
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Address 0
Register Digital correction registers
Bit 3 DT3 DT_ON
Bit 2 DT2 DT6
Bit 1 DT1 DT5
Bit 0 DT0 DT4
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These registers enable and set the level of digital correction applied to oscillator clock. DT_ON enables the correction function, and bits DT0 to DT6 set the level of correction to be applied. This function adjusts the number of 1 second cycles which occur every 10 seconds. When digital correction is not used, a 0 should be written to DT_ON to disable correction. Correction range and resolution (correction range depends on the frequency)
Correction range -195.20 to +192.15ppm Correction resolution 3.05ppm Correction cycle 10 seconds
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DT bits and digital correction (correction value depends on the frequency)
Digital correction bits Correction (ppm) DT6 0 0 DT5 1 1 DT4 1 1 DT3 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 DT2 1 1 DT1 1 1 DT0 1 0 +192.15 +189.10 +6.10 +3.05 0.00 -3.05 -6.10 -192.15 -195.20
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Correction value calculation * Positive correction (leading time) [DT6:0] = correction / 3.05 (with decimal round-off) Example: for correction of 192.15ppm [DT6:0] = 192.15 / 3.05 = 6310 = 01111112 * Negative correction (lagging time) [DT6:0] = 128 + correction / 3.05 (with decimal round-off) Example: for correction of -158.6ppm [DT6:0] = 128 + (-158.6 / 3.05) = 7610 = 10011002
SEIKO NPC CORPORATION --20
SM8580AM
INTERRUPT OPERATION
Alarm Interrupt
When AIE is 1 and an alarm event occurs (AF bit is set to 1), AIRQN output goes LOW. If AIE is 0, however, AIRQN is in a high-impedance state. The alarm interrupt is output when a carry from the seconds register to the minute register occurs.
"1" AIE bit "0" AIRQN pin
"1"
"1" *No output while AIE bit is "0". Hi-Z "L" level "1"
"0"
AF bit "0" Interrupt is active. Setting AF bit to "0".
Timer Interrupt
The timer interrupt mode (level interrupt or periodic interrupt) is selected by the setting of TI/TP. Level interrupt mode (TI/TP = 0) When TIE is 1 and a timer interrupt event occurs (TF bit is set to 1), TIRQN goes LOW. When TIE is 0, however, TIRQN is in a high-impedance state.
"1" TIE bit "0" TIRQN pin
"1"
"1" *No output while TIE bit is "0". Hi-Z "L" level "1"
"0"
TF bit
"0" Interrupt is active. Setting TF bit to "0".
SEIKO NPC CORPORATION --21
SM8580AM Periodic interrupt mode (TI/TP = 1) When TIE is 1 and a timer interrupt event occurs (TF bit is set to 1), TIRQN goes LOW. If TIE is 0, however, TIRQN is in a high-impedance state, and the TF bit remains set to 1.
"1" TIE bit "0"
tRTN
TIRQN pin Auto-return
Hi-Z "L" level
"1" TF bit "0" Interrupt is active. Setting TF bit to "0".
The auto-return time (tRTN), shown in the following figure and table, is determined by the source clock frequency set by register 8 in bank 2 bits TD0 and TD1.
Source CLK
Hi-Z TIRQN pin "0" Auto return time (tRTN) Interrupt cycle
TD1 0 0 1 1
TD0 0 1 0 1
Source clock 4096Hz 64Hz 1Hz 1/60Hz
Auto-return time (tRTN) 0.122ms 7.81ms 7.81ms 7.81ms
SEIKO NPC CORPORATION --22
SM8580AM
APPLICATION NOTES
Setting the Alarm
Alarms can be set for day, weekday, hour, minute, and second. However, it is not possible to set an alarm for more than one weekday. Note that it is recommended that AF and AIE be set to 0 at the same time to avoid accidental hardware interrupts while setting the alarm. After the alarm data is entered, initialization occurs when AF is again set to 0. If the interrupt output is not used by setting AIE set to 0, an alarm can still be controlled by software monitoring of the AF bit. Example 1 To set an alarm for 6pm of the following day: * Set bits AIE and AF to 0. * Set the day register AE bit to 1. * Acquire the current weekday setting from bank 0 register 6, add 1 to the current value (except in the case of Saturday), and write the updated data. Note that the day following 6H (Saturday) is 0H (Sunday). * Write 18H to the hour alarm register. * Write 00H to the minute alarm register. * Write 00H to the seconds alarm register. * Set bit AF to 0. * Set bit AIE to 1. Example 2 To set an alarm for 6am on every for Sunday: * * * * * * * * Set bits AIE and AF to 0. Set the day alarm register AE bit to 1. Write 0H to the weekday alarm register. Write 06H to the hour alarm register. Write 00H to the minute alarm register. Write 00H to the seconds alarm register. Set bit AF to 0. Set bit AIE to 1.
Using the Temperature Sensor
The SM8580AM temperature sensor can be used to monitor the surrounding temperature. The temperature sensor information can then be used to adjust the clock for any temperature variations in the oscillator frequency which affect the accuracy of the clock. One method of utilizing the temperature sensor to adjust timing errors is by using the clock error correction function (digital correction), as described below. 1. Based on the known temperature characteristics of the oscillator crystal, store temperature correction values for various temperatures in an external non-volatile EEPROM. 2. Use an A/D converter, such as in a general-purpose CPU, to convert the VTEMP temperature sensor output voltage into a digital value. 3. Use the digital value of the current temperature to access the temperature correction data stored in the EEPROM, and then write the corresponding data into the digital correction registers. This procedure is useful in implementing a high-accuracy clock function.
SEIKO NPC CORPORATION --23
SM8580AM
Monitoring Digital Correction
Using the test mode allows the 64Hz digital correction clock to be output on pin FOUT. The test mode works as follows. Apply a HIGH-level on FCON. Set the FOUT frequency set register FE bit to 1. Set the CE1 control register CDT_ON bit to 1. Set correction data in the digital correction register DT0 to DT6 bits, and then set DT_ON to 1. Set the bank 2 register C, bit 1 to 1. When CE0N is LOW and CE1 is HIGH and the test mode set register TEST bit is set to 1, the digital correction cycle changes from 10 seconds to 1/64 seconds, and the clock output on FOUT is the 64Hz clock after timing correction. The output is the corrected timing for the set digital correction value corresponding to a 64Hz clock x 64[ppm]. Measuring this output provides a quick method for monitoring the digital correction function. 7. When CE0N goes HIGH, the TEST bit is reset to 1 and test mode is released. 1. 2. 3. 4. 5. 6.
TYPICAL APPLICATION CIRCUIT
VCC Schottky Barrier Diode VDD FOUT VTEMP AIRQN XT TIRQN CE1 CE0N XTN A0 to A3 D0 to D3 FCON RDN WRN VSS Address Decoder Upper Address A0 to A3 D0 to D3 RDN WRN VSS VCC Voltage Detector
CPU
SM8580AM
Note. Because all the circuit components, except the crystal unit, are built in the SM8580AM chip, the oscillation circuit is realized just by the connection of the 32.768kHz crystal unit between XT and XTN terminals. The digital correction function is used to adjust the accuracy of clock time.
SEIKO NPC CORPORATION --24
SM8580AM
Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter "Products") are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter "NPC"). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: sales@npc.co.jp
NC9915FE 2006.06
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